I cant compile this VHDL code because of z but i dont know why and how to fix it

Question

Im getting this error in compiling this VHDL code with ModelSim:

** Error: testVHDL_5.vhd(14): Cannot read output "z".
#   VHDL 2008 allows reading outputs.
#   This facility is enabled by compiling with -2008.

VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity gate_1 is
    port(
        a, b, c : in std_logic;
        x, z : out std_logic
        );
end gate_1;

architecture arch1 of gate_1 is 
begin -- rt1
    z <= b or c;
    x <= a and b and z;
end arch1;

testVHDL_5 is the name of my file. I know in the problem is that z cant be used in x. Can someone explain why and suggest a solution. Thanks.

Answer 1

You can use an internal signal to assign (b or c) and use that for calculating x.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity gate_1 is
  port(
    a, b, c : in  std_logic;
    x, z    : out std_logic
    );
end gate_1;

architecture arch1 of gate_1 is
  signal temp : std_logic;
begin 
  temp <= b or c;
  x    <= a and b and temp;
  z    <= temp;
end arch1;

You don't need to enable VHDL 2008 for this.

As @oldfart said, Please do not use x,z. Use meaningful names.