Verilog, comparison to not equal bit of variable

Question

I wonder if there is a possible way to comparison below variables.

reg [7:0] var1;
reg [3:0] var2;

Here I want to check if var2 is equal to last 4 bits of var1. Can I do that? If yes, how?

Answer 1

Like so:

if (var1[3:0] == var2)
    ...