I've tried to delay in the initial but it doesn't work I'm a newbie in Verilog and it was a training problem
I get x at clk_o2 if I change it on the negative edge
I think you are referring to the last always block in the clkdivisor module. The problem is your testbench produces a negedge clk at time 0 because it code from X to 0. That creates a race with the initial block trying to assign clockout2 to 0.
You can get rid of the race by using a blocking assignment. initial begin clockout1 = 0; clockout2 = 0; end
Your code is certainly not synthesizable. There are other ways of fixing this, but we don't know exactly what is supposed to do.
