Is there a way to make signals in Chisel not defined at module scope visible in waveforms?

Question

If we take for example the following code excerpt (at the top of a module):

val write_indices = WireInit(VecInit(Seq.fill(wordsPerBeat)(0.U((log2Ceil(nWays)+log2Ceil(nSets)+log2Ceil(cacheBlockBytes/wordBytes)).W))))
val write_line_indices = WireInit(VecInit(Seq.fill(wordsPerBeat)(0.U(log2Ceil(cacheBlockBytes/wordBytes).W))))
dontTouch(write_indices)
dontTouch(write_line_indices)
// refill logic
when(mem_response_present) {
  for (i <- 0 until wordsPerBeat) {
    val beatIdx = i.U(log2Ceil(wordsPerBeat).W)
    val write_line_index = Cat(d_refill_cnt(log2Ceil(cacheBlockBytes/wordsPerBeat/wordBytes)-1, 0), beatIdx)
    val write_idx = Cat(refill_way, refill_set, write_line_index)
    write_indices(i) := write_idx
    write_line_indices(i) := write_line_index
    cache_line(write_idx) := tl_out.d.bits.data((i + 1) * wordBits - 1, i * wordBits)
  }
}

The only reason for the two top level signals is to get lower signals visible in waveforms. Is there any way to achieve the same effect without having to manually create those signals? In this example half the code is used just to get the ability to debug. That seems a bit excessive.

Answer 1

That seems a bit excessive

Completely agreed, fortunately there is a solution. For implementation reasons, Chisel by default is only able to name public fields of the Module class. That is, only the values at the the top-level scope of your Module. However, there is a nifty macro chisel3.experimental.chiselName that can name these vals inside of the for loop. Try annotating your Module like so:

import chisel3._
import chisel3.experimental.chiselName

@chiselName
class MyModule extends Module {
  ...
}

Please check out this earlier answer discussing naming, it has more information than is relevant to answer this question alone, but it has other useful information about how naming works in Chisel.