in makefile echoing "compiling" before the compilation

Question

i thought it would be easy but i can't actually figure out nor find on internet, a solution to advertise "compilation of the objects file" (for instance) just before compiling, and avoiding relink in the same time

my makefile would be something like this :

    libfrog.a: $(OBJS)
        @echo "building the library"
        ar -rc $@ $^
    %.o:%.c
        gcc -i. -c -o $@ $<

which produce, when prompt "make" :

    gcc -I. -c -o file01.o file01.c
    gcc -I. -c -o file02.o file02.c
    gcc -I. -c -o file03.o file03.c
    gcc -I. -c -o file04.o file04.c
    gcc -I. -c -o file05.o file05.c
    building library
    ar -rc libfrog.a file01.o file02.o file03.o file04.o file05.o

but i would like to have :

    compilation of the objects files
    gcc -I. -c -o file01.o file01.c
    gcc -I. -c -o file02.o file02.c
    gcc -I. -c -o file03.o file03.c
    gcc -I. -c -o file04.o file04.c
    gcc -I. -c -o file05.o file05.c
    building library
    ar -rc libfrog.a file01.o file02.o file03.o file04.o file05.o

now :

1 - if i put an echo before the rule libfrog.a is called (say by creating another first rule), it will print even if i prompt "make" two times and nothing is to be done...

2 - if i put an echo in the rule %.o:%.c it will print for each file

3 - if i put an echo as a dependency of the first rule it will force to relink all the files when prompt "make" again, even when just one file has been modified libfrog.a: echo $(OBJS) (and a rule "echo" which echo the text)...

so I've tried to echo for each compilation but with changing the text to echo nothing, i failed... i tried to create an echo.txt file just to create a rule that would depend on its existence but i failed too. I have no idea if it's possible ?

Answer 1

It's not really simple to do. But if you're using GNU make you can do it with the help of order-only prerequisites:

%.o : %.c | announce
        gcc -I. -c -o $@ $<

.PHONY: announce
announce:
        echo "compilation of the objects files"

Personally I don't think showing this message is needed and I wouldn't add even the above amount of complexity to support it in my makefiles.

But if you really want to do it and you don't want the message to be printed unless some object file needs to be made, you'll have to get really fancy and do something like this:

PRINTED :=

%.o : %.c
        $(or $(PRINTED),$(eval PRINTED := :)echo "compilation of the objects files")
        gcc -I. -c -o $@ $<     

Once it's working you'll want to add a @ before the first recipe line.