I am trying to read the output from multiple components and display them within an integer form. The outputs are all 4-bit vectors. As I do not want to have to repeat the code numerous times, I am trying the use of functions native to VHDL. I have not used these before and also cannot see much well-explained documentation online.
function FourBitsToNumber (X : std_logic_vector(3 downto 0))
return integer is
begin
if (X = "0000") then return 0;
elsif (X = "0001") then return integer(1);
elsif (X = "0010") then return integer(2);
elsif (X = "0011") then return integer(3);
elsif (X = "0100") then return integer(4);
elsif (X = "0101") then return integer(5);
elsif (X = "0110") then return integer(6);
elsif (X = "0111") then return integer(7);
elsif (X = "1000") then return integer(8);
elsif (X = "1001") then return integer(9);
end if;
end FourBitsToNumber;
I am calling the function on the clock pulse with the following code:
variable1 <= FourBitsToNumber(A);
...With 'variable1' being of type integer declaration. 'A' is a 4-bit vector.
However, from my test bench, I can see that the line of code is being reached but am just receiving a value of 0 throughout (even when I know it should be more).
My guess is maybe the syntax or another stupid error on my behalf.
Try this...
function my_int(X : std_logic_vector(3 downto 0)) return integer is
begin
return to_integer(unsigned(X));
end function my_int;
I have a feeling that this could also work with an undefined length slv... e.g.
function my_int_of_any_len(X : std_logic_vector) return integer is
begin
return to_integer(unsigned(X));
end function my_int_of_any_len;
Matthew's suggestion: (see his comment below)
function my_int(X : std_logic_vector(3 downto 0)) return integer is
use ieee.numeric_std.all;
begin
return to_integer(unsigned(X));
end function my_int;
I should also point out that you dont actually have to build your own function for this. Where you have said that you want an integer, just put variable1 <= to_integer(unsigned(X));