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vhdl

Does if generate support else?

I've been searching but couldn't find any useful information so I guess it's not supported...

I have a construct like

SIGNAL container : STD_LOGIC_VECTOR((2*total)-1 DOWNTO 0);
SIGNAL storage : STD_LOGIC_VECTOR(total-1 DOWNTO 0);
copy : FOR a in 0 to total-1 GENERATE
    first_set : IF a < 10 GENERATE
        storage(a)  <= container(a);
    END GENERATE;
    second_set : IF a > 9 GENERATE
        storage(a)  <= container(a+10);
    END GENERATE;
END GENERATE;

So I'd like to concatenate two subvectors into a new one, but is there a way to use ELSE if the first_set condition is False? Something like

SIGNAL container : STD_LOGIC_VECTOR((2*total)-1 DOWNTO 0);
SIGNAL storage : STD_LOGIC_VECTOR(total-1 DOWNTO 0);
copy : FOR a in 0 to total-1 GENERATE
    first_set : IF a < 10 GENERATE
        storage(a)  <= container(a);
    ELSE
        storage(a)  <= container(a+10);
    END GENERATE;
END GENERATE;
Solution

  • If..elsif..else generate was added in vhdl 2008. Case..generate was also added.