I am a FPGA beginner and recently I tried a very simple flowing-light program that went well on my computer. However, the LEDs on my Zybo remain the initial state(only the leftmost LED lights up) no matter how long I wait. I searched for the solution for a week and tried any way I can think of even borrowed another board from my friend, yet the problem just exists.
Here's my verilog code
top.v
module top(
input clk,
output [3:0] led
);
reg [23:0] cnt_reg;
reg [3:0] led_reg;
initial begin
cnt_reg <= 0;
led_reg <= 4'b1000;
end
always @(posedge clk)begin
if(cnt_reg == 24'h00000f)
begin
if(led_reg == 4'b0001)
led_reg <= 4'b1000;
else
led_reg <= led_reg>>1;
end
else
cnt_reg <= cnt_reg + 1;
end
assign led = led_reg;
endmodule
Here's my constraint
set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1
set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk
Here's my testbench
`timescale 1ns/1ps
module tb();
reg clk;
wire [3:0] led;
top U0 (.clk(clk), .led(led));
parameter Period = 10;
always begin
clk = 1'b0;
#(Period/2) clk=1'b1;
#(Period/2);
end
initial begin
clk = 1'b0;
#1000000;
end
endmodule
And the simulation result shows below: the simulation result
After programming my device LEDs just remain the initial state
After programming my device LEDs just remain the initial state
Your LEDS do not remain in the init state because all four of them light up. In the init state you have "1000". Which would be one on and three off (or vice versa depending on on how they are connected).
What is happening is that you board behave just like your simulation result shows you: every clock cycle the next LED lights up. Your clock is probably around 10MHz or 100MHz so you don't see that.
To fix this you need two things:
You need to count longer. How big depends on your clock frequency so find out what it is.
Fix your counter code. Once the counter value is reached it no longer counts. It stays at 24'h00000F. You waveform does not show that but your code is obvious.