In VHDL, how to check a case statement value partially meets some signal values and the rest don't matter?

Question

case (my_state_val & val_q) is
    when ("000" & "00") => do something;
    when ("001" & "00") => do something else;
    when ("010" & "10") => do a 3rd thing;
    when ("100" & "DONT CARE") => do a non-default thing because my_state_val is valid;
    when others => default state or null;
end case;

If it was an if check, I could do: val_q /= "11" because I know my counter will never reach the top value. How can I do this in a case statement?

The reason why I want a case statement is because I don't want a 30+ depth branches.

if 1 then
elsif 2 then
...
elsif 25 then
elsif 26 then
elsif 27 then
else
end if;

Answer 1

I would suggest either this:

case (my_state_val & val_q) is when ("000" & "00") => do something; when ("001" & "00") => do something else; when ("010" & "10") => do a 3rd thing; when others => if my_state_val == "100" then do a non-default thing because my_state_val is valid else default state or null; end if; end case;

Or this:

case (my_state_val) is when ("000") => Evaluate val_q; when ("001") => Evaluate val_q; when ("010") => Evaluate val_q; when ("100") => Evaluate val_q; when others => default state or null; end case;