Sub-module not found after changing parameter through chparam in a foreach loop

Question

I am trying to synthesize a module for different values of a parameter. I am changing the parameter with a foreach loop in tcl and passing the updated parameter to the top module using -chparam tag in the hierarchy command. It works for the first iteration of the loop. However, in the second iteration, it shows the error that one of the sub-modules is not found.

I have written a simple module (written in test.sv) to demonstrate the problem.

module top #(parameter N = 8)(
    input [N-1:0] x,
    output y
);

    isZero #(.N(N)) isZero_inst(
        .x(x),
        .y(y)
    );

endmodule


module isZero #(parameter N = 8)(
    input [N-1:0] x,
    output y
);

    assign y = |x;

endmodule

I am using the following tcl command (written in test.tcl):

yosys -import

read_verilog -defer -sv  test.sv 

foreach N [list 4 8] {
    hierarchy -check -top top -chparam N $N 
    procs; opt; 
    flatten; opt; 
    techmap; opt;
    abc; opt; 
    clean; opt;
    opt_clean -purge
    write_verilog -noattr -noexpr test_${N}_syn.v
}

It generates the first file: test_4_syn.v. However, in the second iteration, it shows the error:

Module `\isZero' referenced in module `\top' in cell `\isZero_inst' is not part of the design.

For completeness: I am using the following command to run the tcl file:

yosys -c test.tcl

Answer 1

hierarchy is the main part of elaboration, and IIRC will purge non-parameterised versions of parameterised modules.

The design command is a good way of dealing with this without re-running read_verilog. e.g.:

yosys -import

read_verilog -defer -sv  test.sv 
design -stash test

foreach N [list 4 8] {
    design -load test
    hierarchy -check -top top -chparam N $N 
    procs; opt; 
    flatten; opt; 
    techmap; opt;
    abc; opt; 
    clean; opt;
    opt_clean -purge
    write_verilog -noattr -noexpr test_${N}_syn.v
}