Adding cell to write_verilog causes error

Question

first of all, I'd like to say I'm not well versed in c++ or verilog at all, so I have a few problems implementing things in Yosys.

I'm currently looking for a way to implement a naive information flow tracking approach to write_verilog. The way I intent to implement it, is by creating a new var for each input/output etc. All operations types will be exchanged with simple 'or's. The doubled variables serve as taint bits. Doubling all the wires was an easy task. However when I try to add a new cell, I run into a 'std::out_of_range' error (edit: just as I was trying it again, it appears to be an 'Found error in internal cell' error now) while dumping the module. As the error happens while calling the dump_module function, I assume the module model broke.

What I've done is that for every wire in the module, I've added the same wire just with '_taint' appended to its name, its properties stays the same as the original wire, I've basically used a slightly modified version of add_wire from /passes/add.cc.

// adding taint wires

void attach_ift(RTLIL::Module *module, bool precise)
{

    auto wires = module->wires_;
    for (auto &wire : wires){
        std::string ift_wire_name = RTLIL::id2cstr(wire.second->name) + std::string("_taint");
        add_wire(module, ift_wire_name, 1, wire.second->port_input, wire.second->port_output);
    }

    //add cells and connections

}

static void add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output)
{
    RTLIL::Wire *wire = nullptr;
    name = RTLIL::escape_id(name);

    if (module->count_id(name) != 0)
    {
        wire = module->wire(name);

        if (wire != nullptr && wire->width != width)
            wire = nullptr;

        if (wire != nullptr && wire->port_input != flag_input)
            wire = nullptr;

        if (wire != nullptr && wire->port_output != flag_output)
            wire = nullptr;

        if (wire == nullptr)
            log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());

        log("Module %s already has such an object.\n", module->name.c_str());
    }
    else
    {
        wire = module->addWire(name, width);
        wire->port_input = flag_input;
        wire->port_output = flag_output;

        if (flag_input || flag_output) {
            module->fixup_ports();
        }

        log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
    }
}

This works fine.

Now for the problem with cells. How do I add cells properly?
at first I tried to use

//add cells

void attach_ift(RTLIL::Module *module, bool precise)
{
    // add wires

    auto cells = module->cells_;
    for (auto &cell : cells){
        std::string ift_cell_name = cell.first.c_str() +std::string("_taint");
        auto cell_ = cell.second;
        add_cell(module, ift_cell_name, cell_);
    }

    // add connections
}

static void add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output)
{
    RTLIL::Wire *wire = nullptr;
    name = RTLIL::escape_id(name);

    if (module->count_id(name) != 0)
    {
        wire = module->wire(name);

        if (wire != nullptr && wire->width != width)
            wire = nullptr;

        if (wire != nullptr && wire->port_input != flag_input)
            wire = nullptr;

        if (wire != nullptr && wire->port_output != flag_output)
            wire = nullptr;

        if (wire == nullptr)
            log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());

        log("Module %s already has such an object.\n", module->name.c_str());
    }
    else
    {
        auto ift_cell = module->addCell(name, "$or");
        auto cons = cell->connections();
        for (auto con : cons){

            auto wire_ = cell->getPort(con.first).as_wire();
            auto taint_wire_name = string(wire_->name.c_str()) + "_taint";
            auto wire = module->wire(taint_wire_name);
            ift_cell->setPort(taint_wire_name, wire);
        }

        log("Added cell %s to module %s.\n", name.c_str(), module->name.c_str());
    }
}

I attach the ift function right before I dump the module, so at this point

    void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
    {

        // some code

        for (auto module : design->modules()) {

            //more code

            log("Attaching ift annotations to `%s'.\n", module->name.c_str());
            attach_ift(module, precise);

            log("Dumping module `%s'.\n", module->name.c_str());
            dump_module(*f, "", module);
        }

        auto_name_map.clear();
        reg_wires.clear();
    }

I then thought maybe I failed at setting proper connections. However even just adding a simple module->addCell("$dummyName", "$or"); crashed my program.

Can someone please help me?

Answer 1

Internal cells, beginning with $, have a particular contract they must follow in terms of ports, parameters etc and that an empty cell won't fulfil. Use functions like addOr rather than addCell to create these.