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verilogmodelsim

Output of D flip-flop not as expected

It is async reset. D flipflop when i change reset from one to zero, it doesn't immediately raise the output from zero to one. but when i add in @always ( posedge clk or posedge reset or negedge reset ) it immediately change

Verilog:

module dff_async_reset (
data   , // Data Input
clk    , // Clock Input
reset  , // Reset input
q        // Q output
);
//-----------Input Ports---------------
input data, clk, reset ; 

//-----------Output Ports---------------
output q;

//------------Internal Variables--------
reg q;

//-------------Code Starts Here---------
always @ ( posedge clk or posedge reset)
begin
if (reset) 
  q =0;
else 
  q <= data;
end

endmodule //End Of Module dff_async_reset

Corresponding waveform:

waves

Solution

  • It does exactly what you tell it to do: mimic a flip-flop with an asynchronous active-high reset. The following line from your code

    always @ (posedge clk or posedge reset)

    says: "execute this procedural block when clk makes the transition 0 --> 1 or when reset makes the transition 0 --> 1." In other words, when reset makes the transition 1 --> 0, this always block will not be evaluated.

    You value q will only be updated on the positive edge of clk, which is exactly what you want if you want to design a flip-flop.

    When you add negedge reset to your sensitivity list, it will indeed immediatelly change when you go out of your reset state (which is 1 --> 0 in your logic). This is, however, usually not desired. Rather, you should synchronize the deassertion of your reset to your clock signal. To quote from the aforementioned website:

    The way most of the designs have been modelled needs asynchronous reset assertion and synchronous de-assertion. The requirement of most of the designs these days is:

    • When reset is asserted, it propagates to all designs; brings them to reset state whether or not clock is toggling; i.e. assertion should be asynchronous
    • When reset is deasserted, wait for a clock edge, and then, move the system to next state as per the FSM (Finite State Machine); i.e. deassertion should be synchronous