how to pack zeros in to bundles in chisel

Question

I have a question on pack zeros into bundles. For example consider the next code:

    class CmplxNum(val bitwidth: Int) extends Bundle {
       val real = SInt(INPUT,bitwidth.W)
       val imag = SInt(INPUT,bitwidth.W)
    }  

    class MyClass extends Module {
       val io = IO(new Bundle {
          val in = new CmplxNum(16)
          val load = Bool(INPUT)
          val clr  = Bool(INPUT)
          ...
       })
       ...
       val sample = RegEnable(io.in,0.S,io.load) // <-- how do i set the reset value     
       When(io.clr) {
          sample <> sample.fromBits(0.S) // <-- I tried this it compiles, but dont know if it is correct  
       }

    }

How do I pack zeros into this Bundle in the RegEnable & clr cases ? For RegEnable I've got elaboration error of type miss-match which make sense

Answer 1

Here is one way. It relies on the relatively new BundleLiterals (new CmplxNum(16)).Lit(_.real -> 0.S, _.imag -> 0.S). I have also refactored your code a little bit to use the current chisel3 idioms. Without a specific need I would not recommend placing your Input/Output in Bundle. Also the more modern way is to wrap the IO fields in Input() or Output()

import chisel3._
import chisel3.util.RegEnable
import chisel3.experimental.BundleLiterals._


class CmplxNum(val bitwidth: Int) extends Bundle {
  val real = SInt(bitwidth.W)
  val imag = SInt(bitwidth.W)
}

class MyClass extends Module {
  val io = IO(new Bundle {
    val in = Input(new CmplxNum(16))
    val load = Input(Bool())
    val clr  = Input(Bool())
      ...
  })

    ...
  val sample = RegEnable(
    io.in,
    init = (new CmplxNum(16)).Lit(_.real -> 0.S, _.imag -> 0.S),
    enable = io.load
  )
  when(io.clr) {
    sample <> sample.fromBits(0.S) // <-- I tried this it compiles, but dont know if it is correct
  }

}