I am wondering if it is possible to use Yosys in simplifying logic equations.
For example:
module top
(
output [31:0] cipher,
input [31:0] plain,
input [63:0] key
);
wire tmp = key[31:0];
wire tmp2 = key[63:32] & 0;
assign cipher = (tmp & plain) | tmp2;
endmodule
When I use the command "show" it plots the circuit:
I tried using "opt" and "freduce" commands but it did not reduce the equation.
You probably want to use opt -fine
which does finer-grain optimisations rather than optimising whole words at a time. This gives a single 1-bit $and
gate as expected.
Alternatively techmap; abc
will produce an optimised gate-level circuit.