VHDL way to group constants together

Question

Is it possible to group related constants together inside of packages? What I want to do is to have generic constants but then grouped together with related constants and types. In software like Python this could be done with package inside of package or class to group constants together.

What I want to do is something like this:

library constants;
...
if (some_signal = constants.group_a.SOME_CONSTANT_VALUE) then
    ...
end if;

Reader can see where the constant is coming from like here group_a.

Answer 1

If I understand the question well you can use records inside your package

package ex_pkg is

  type constants_group_1_t is record
    CONSTANT1 : integer;     
    CONSTANT2 : integer;
    CONSTANT3 : integer;
    CONSTANT4 : integer;
  end record constants_group_1_t;

constant constant_group1 : constants_group_1_t  := (
 CONSTANT1 => 1,
 CONSTANT2 => 2,
 CONSTANT3 => 3,
 CONSTANT4 => 4
);

end package;

then you can use it as

liberary work;

...

 if some_integer = work.ex_pkg.constants_group1.CONSTANT1 then

 end if; 

so basically you declare a new record type containing all the constants that you want to use, which can be any of your chosen types, then creating a constant of the newly created type and assign for each field its value. You can then access it like "record.field" moreover you can define a record of records for as deep abstraction as you want.