I am working on an Ethernet driver for the Digilent Nexys4 board (Artix7 FPGA). I have written a VHDL component to communicate with the LAN8720A PHY in MDIO protocol. It works well, When I send a frame asking to write in a register, I can read the value I wrote. But when I ask to read the Basic Status Register, it returns a link down status.
That means the Ethernet link is down and I cannot send Ethernet frames. I have absolutely no idea of why I have the link down status. Even when I let the auto-negociation enabled, after the auto-negiacion is over when I try to send a frame, I have a link down status.
Does anyone have an idea of why this is happening and maybe how I can fix this ?
Thanks.
EDIT : it seems it is because of the DATA_VALID signal of the LAN8720A. Does anyone know how can I set the signal to '1' ?
EDIT2 : for more precisions, DATA_VALID is an internal signal of the LAN8720A. It is used to pull up or down the link state bit of the status register.
I have found a solution to my problem : I did not respect the interframe time. Now that I respect the interframe time, the link state does not go down, it stays up. Though the frame is still not sent, it is a great step forward.