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if-statementvhdl

Trying to finish adder need if statement to change carry

I have got an adder with inputs a and b in std_logic_vector(data_width-1) downto 0 and out output of sum std_logic_vector(data_width) downto 0. I am trying to use an if statement to bypass the carry bit and add it to the sum

I just need help with the syntax the idea is if the carry's MSB is 1 the it adds 1 to the answer(sum)

architecture v1 of adding is
begin
adding : process (A, B) is
    variable CI :  std_logic_vector((DATA_WIDTH) downto 0);
    variable SUMMER :  std_logic_vector((DATA_WIDTH) downto 0);
begin   
            SUMMER := A xor B;
            CI := A and B;
            CI_msb <= CI(CI'left);
            if CI_msb =  '1' then
                SUMMER = SUMMER + 1;
            end if;

I am getting syntax errors regarding (summer = summer + 1;) I am not familiar enough to know what is needed.

Solution

  • To assign a value to a variable you have to use :=, so the code becomes SUMMER := SUMMER + 1;.