Case statement in VHDL test bench takes decremented value

Question

I am working on a project using VHDL and I am facing a problem during one of my test benches. I testing all input combinations for a combinational component using a for loop in my stimulus process, but I have a case statement inside the foor loop which is not behaving the way I wish it to.

This is the code segment that isn't behaving the way I want it to:

for i in 0 to 20 loop
    case opcode is
        when "01001" | "01010" | "01100" | "01110" | "10000" =>
            d <= '0';
            wait for period;
            d <= '1';
        when "00010" | "00100" | "00101" | "00110" | "10001" | "10010" | "10011" =>
            d <= '1';
        when others =>
            d <= '0';
    end case;
    wait for period;
    opcode <= opcode + 1;

end loop;

As an example, I expect d to become 1 when opcode is 00010. In the simulation, however, d becomes 1 when opcode becomes 00011 rather than 00010 (same for all other cases too), as if the value the case statement checks is decremented by 1. I changed opcode inside the case statement to opcode+1 and it worked correctly. I do know that VHDL is a hardware description language and that its behavior differs from a programming language, but I still cannot wrap my head around why this is happening, and would like an explanation.

Answer 1

The update to the opcode signal is not 'sensed' by the simulator until it hits a wait statement. Adding wait for 0 ns; at the start of the loop fixes the problem.