vivado block designer not updating RTL interface in block design after modifying verilog or vhdl RTL files
I would swear that vivado has a bug in that it never refreshes any interface changes made to an RTL file, verilog or vhdl, after it has been pasted into the "block design" with "add module"....
What the secret to get Vivado block designer to see file changes made to the interface of verilog or vhdl files imported into a "block design"?
Then you try to brute force it by deleting the "rtl module" from the block design, but somehow its still cached and doens't see it, so then you end up destroying your project and setting it up again because vivado is such POS tool...
So my question is where is the secrete reset button in the software to get it to see rtl interface changes in the "block design" without out obliterating your vivado project and starting over again?
is it some tool command or menu item you need to select?
To Refresh RTL after updating it in IP integrator:
Select RTL block in IP Integrator, right click on it and select "Refresh Module".
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