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vhdlfpgahdl

i have some problem about current time in vhdl

I am the first student to start vhdl recently. It is currently working on the FPGA board. I wish my seven-segment would have the current time whenever I pressed the RESET button. Is there a way to solve it?

I searched stackoverflow all day. but i can not find solution..

  -- Time information
  constant HOUR_INT   : integer                       := 00;  --  I think we should put the current time in here.
  constant HOUR_HEX   : std_logic_vector(7 downto 0)  := X"00";
  constant MINUTE_INT : integer                       := 00;
  constant MINUTE_HEX : std_logic_vector(7 downto 0)  := X"00";

if reset = '0' then
      hour <= conv_std_logic_vector(datetime.hour_int, 5)

in this code proportion, why i have to input 5 next to hout_int?

Solution

  • I think it isn't possible to get the current time of the system (considering the attempts / questions of other people on this forum). So it's also impossible to use reset for get the current time.

    Maybe it's usefull to take a look here

    someone who has already tried it in a different way with an RTC (with success): - here non-manually set clock - here manually set clock