I am fairly new to VHDL and I am running some snippets from a code I was given to see what it is doing. There is a custom array type I want to see in the console, but I get and error when I try to write it.
entity hello_world is
end entity hello_world;
library STD;
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
architecture test of hello_world is
type row_type is array(0 to 2) of std_logic_vector(3 downto 0);
type new_type is array(0 to 1) of row_type;
signal max_new : new_type := (others => (others => (others => '0')));
begin
my_print : process is
variable my_line : line;
begin
write(my_line, string'("Value of max_new"));
write(my_line, max_new);
writeline(output, my_line);
wait;
end process my_print;
end architecture test;
The error I get while running the simulation is:
Error: type error near 'max_new': expected type 'std_ulogic'. Error: formal 'l' of mode inout must have an associated actual. Error: formal 'value' has no actual or default value. Error: indexed name prefix type 'void' is not an array type
If I understood correctly, row type is an array of size 3, in each position I have a vector made of 4 bits. new_type is an array of size 2, in each position I have a row_type, which is an array of size 3 with a 4 bits vector in each position. Is this correct? Since it is initialized to 0, I expect to see only that.
I am using Vivado 2018.3 for the simulation.
Any help would be highly appreciated!
The function write of std.textio can take the following arguments as value (https://www.hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/TEXTIOPackage.htm) :
IEEE.std_logic_textio add std_logic and his derivated to this list but Array is not handled by write.
You can print your array like that :
my_print : process is
variable my_line : line;
begin
write(my_line, string'("Value of max_new"));
for I in 0 to 1 loop
for J in 0 to 2 loop
write(my_line, max_new(I)(J));
end loop;
end loop;
writeline(output, my_line);
wait;
end process my_print;