I have a state machine with 3 states. Each state has specific output values associated with it. During synthesis, I get a warning if I don't assign the outputs in the 4'th state. There is no transition to the 4'th state so it is unreachable. What outputs should I assign in the 4'th state?
I saw an example on the internet where they assigned "Unknown value". Does this improve performance? Is it dangerous in some way?
reg [1:0] state;
reg [7:0] out;
always @(state) begin
case (state)
2'b00: out = 8'hAA;
2'b01: out = 8'hBB;
2'b10: out = 8'hCC;
default: out = 8'bxxxx_xxxx;
endcase
end
I saw an example on the internet where they assigned "Unknown value". Does this improve performance? Is it dangerous in some way?
No it is not dangerous. Assigning an unkown value gives a synthesis tool another degree of freedom to optimize. It is, however, important to keep in mind that an unkown state does not exist in silicon. In other words, the synthesis tool will assume a value during this state. The only thing you are indicating is that you don't care about that state.
However, assigning an unknown state in your code is not really necessary. Since you don't care about the 2'b11 state (because it is unreachable), you can simply do the following:
reg [1:0] state;
reg [7:0] out;
always @(state) begin
case (state)
2'b00: out = 8'hAA;
2'b01: out = 8'hBB;
default: out = 8'hCC;
endcase
end
This is probably similar to what a synthesis tool would do.
Please keep in mind that, while assigning an unkown state is synthesizable, comparing to an unkown state is not! The Verilog Hardware Description Language (5th edition) by Thomas & Moorby's explains on page 39 in which way the unkown operator may be used during logic synthesis.