Synth 8-2576 procedural assignment to a non-register trig_i_a is not permitted

Question

I got some issues with my Verilog code. The error is as described in the title. I don't know the source of this error.

Here is my code:

module red_pitaya_trigger_manager(
   input       dac_clk_i,
   input       trig_a_i,
   input       trig_b_i,
   input       master_trig,
   output      trig_out_ch0,
   output      trig_out_ch1
   );

reg trig_out_ch0;
reg trig_out_ch1;

always @(posedge dac_clk_i) begin
   if (master_trig == 1'b1) begin
       trig_a_i <= 1'b0;
       trig_b_i <= 1'b0;
       trig_out_ch0 <= master_trig;
       trig_out_ch1 <= master_trig;
       end
   else if (master_trig == 1'b0) begin
       //master_trig <= 1'b0;
       trig_out_ch0 <= trig_a_i;
       trig_out_ch1  <= trig_b_i;
       end
   end      
endmodule

The actual output of this code is :
[Synth 8-2576] procedural assignment to a non-register trig_i_a is not permitted
[Synth 8-2576] procedural assignment to a non-register trig_i_b is not permitted

Answer 1

There are two problems here. Toolic is right that one of the problems is that you're trying to assign a value to an input and the error message isn't very helpful. But you're getting that error message because of a different problem the tool is noticing first.

When you declare inputs and outputs without a type, they're assumed to be wire by default. And you're assigning to wires in an always block with a <= assignment, which you can only do to reg types. So you're assigning to wires the way you're only allowed to assign to registers, hence the:

[Synth 8-2576] procedural assignment to a non-register trig_i_b is not permitted

If you fixed that by making the input types reg

module red_pitaya_trigger_manager(
   input       dac_clk_i,
   input       trig_a_i,
   input       trig_b_i,
   input       master_trig,
   output      trig_out_ch0,
   output      trig_out_ch1
   );

reg trig_a_i; // note
reg trig_b_i;

reg trig_out_ch0;
reg trig_out_ch1;

always @(posedge dac_clk_i) begin
   if (master_trig == 1'b1) begin
       trig_a_i <= 1'b0;
       trig_b_i <= 1'b0;
       trig_out_ch0 <= master_trig;
       trig_out_ch1 <= master_trig;
       end
   else if (master_trig == 1'b0) begin
       //master_trig <= 1'b0;
       trig_out_ch0 <= trig_a_i;
       trig_out_ch1  <= trig_b_i;
       end
   end
endmodule

Then you'd see the more helpful message when you build:

[Synth 8-6104] Input port 'trig_a_i' has an internal driver

[Synth 8-6104] Input port 'trig_b_i' has an internal driver