VHDL Error(10482) object std_logic_vector is used but not declared

Question

I have written some code about an 8-bit adder using full adders as components. When I start the compilation, it shows one error that I am not able to find. I may have other mistakes that I can't notice.

library ieee;
use ieee.std_logic_1164.all;

entity F_A is
  port(
        a,b,c_in : in std_logic;
        sum,c_out : out std_logic);
end F_A;

architecture behave of F_A is
begin 
  sum <= a xor b xor c_in;
  c_out <= (a and b)or(a and c_in)or(b and c_in);
end behave;

entity Adder_8bit is
  port( a,b: in std_logic_vector(7 downto 0);
        Cin: in std_logic;
        sum: out std_logic_vector(7 downto 0);
        Cout: out std_logic);
end Adder_8bit;

architecture RTL of Adder_8bit is
   signal c : std_logic_vector(7 downto 0);
   component F_A
      port( a,b,c_in : in std_logic;
            sum,c_out: out std_logic);
   end component;
   begin
     FA0 : F_A 
           port map(a(0),b(0),Cin,sum(0),c(0));
     FA1 : F_A 
           port map(a(1),b(1),c(0),sum(1),c(1));
     FA2 : F_A 
           port map(a(2),b(2),c(1),sum(2),c(2));
     FA3 : F_A 
           port map(a(3),b(3),c(2),sum(3),c(3));
     FA4 : F_A 
           port map(a(4),b(4),c(3),sum(4),c(4));
     FA5 : F_A 
           port map(a(5),b(5),c(4),sum(5),c(5));
     FA6 : F_A 
           port map(a(6),b(6),c(5),sum(6),c(6));
     FA7 : F_A
           port map(a(7),b(7),c(6),sum(7),c(7));
     Cout <= c(7);
end RTL;

Here is the error that appears :

Error (10482): VHDL error at Adder_8bit.vhd(17): object "std_logic_vector" is used but not declared

Answer 1

A context clause applies to the following primary design unit (ie entity or package). You need to repeat it before every entity, ie:

library ieee;
use ieee.std_logic_1164.all;

entity Adder_8bit is