I have made a code that does arithmetic and logic operations.But when I do the compilation, the report shows that I have many syntax errors.I am a beginner in VHDL, I really do not know how to correct these mistakes,can you give me some advise?
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.all;
4 use ieee.numeric_std.all;
5
6 package arith_operations is
7 constant size: integer :=8;
8 constant select_bits: integer :=3;
9 procedure add( x,y: in bit_vector(size-1 downto 0);
10 sum: out bit_vector(size-1 downto 0); c_out: out bit );
11 procedure sub( x,y: in bit_vector(size-1 downto 0);
12 d: out bit_vector(size-1 downto 0); c_out: out bit );
13 function inc(x: in bit_vector) return bit_vector;
14 function dec(x: in bit_vector) return bit_vector;
15 end arith_operations;
16
17 package body arith_operations is
18 procedure add( x,y: in bit_vector(size-1 downto 0); sum: out bit_vector(size-1 downto 0);
19 c_out: out bit);
20 variable s: bit_vector(size downto 0);
21 begin
22 s:= "0" & x + "0" & y;
23 sum:= s(size-1 downto 0);
24 c_out:= s(size);
25 end add;
26 procedure sub( x,y: in bit_vector(size-1 downto 0);sum: out bit_vector(size-1 downto 0;
27 c_out: out bit);
28 variable s: bit_vector(size downto 0);
29 begin
30 s:= "0" x + not("0"& y) + ((size-1 downto 0)=>"0") & "1";
31 d:= s(size-1 downto 0);
32 c_out:= s(size);
33 end sub;
34 function inc(x: in bit_vector(size-1 downto 0)) return bit_vector is
35 variable x1: bit_vector(size-1 downto 0);
36 begin
37 x1:= x + ((size-2 downto 0)=>"0") & "1";
38 return x1;
39 end inc;
40
41 function dec(x: in bit_vector(size-1 downto 0)) return bit_vector is
42 variable x1: bit_vector(size-1 downto 0);
43 begin
44 x1:= x + ((size-1 downto 0)=> "1");
45 return x1;
46 end dec;
47 end arith_operations;
48
49 use work.arith_operations.all;
50
51 entity alu is
52 generic(delay :time);
53 port( x,y: in bit_vector(size-1 downto 0);
54 function_select: in bit_vector(size-1 downto 0);
55 f: out bit_vector(size-1 downto 0);
56 end alu;
57
58 architecture behave of alu is:
59 begin
60 p0: process(x,y,function_select)
61 variable f_out: bit_vector(size-1 downto 0);
62 begin
63 case function_select is
64 when "000" => add (x, y, f_out); f<= f_out after delay;
65 when "001" => sub(x, y, f_out); f<= f_out after delay;
66 when "010" => f <= inc(x) after delay;
67 when "010" => f <= dec(x) after delay;
68 when "100" => x or y after delay;
69 when "101" => not x after delay;
70 when "110" => x and y after delay;
71 when "111" => x xor y after delay;
72 end case function_select;
73 end process p0;
74 end architecture behave;
also these are the mistakes :
Error (10500): VHDL syntax error at Alu.vhd(21) near text "begin"; expecting "end", or a declaration statement
Error (10396): VHDL syntax error at Alu.vhd(25): name used in construct must match previously specified name "arith_operations"
Error (10500): VHDL syntax error at Alu.vhd(26) near text "procedure"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
Error (10500): VHDL syntax error at Alu.vhd(56) near text "end"; expecting an identifier ("end" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at Alu.vhd(60) near text ")"; expecting ":", or ","
Error (10500): VHDL syntax error at Alu.vhd(62) near text "begin"; expecting an identifier ("begin" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at Alu.vhd(64) near text ")"; expecting ":", or ","
Error (10500): VHDL syntax error at Alu.vhd(65) near text ")"; expecting ":", or ","
I tried to correct them ,but it looks like some of the errors do not make sense because I have all the punctuation marks that errors show.Also I have set the file as top-evel entity.
There were still a few syntax errors in your code. You should be able to solve them by yourself but some of the notes that I've made:
Declaring a procedure inside a package body should start with e.g. procedure add(...) is. The line should not end with a semicolor, you've done this correctly with functions.
With the expression (size-1 downto 0)=> "1" you've probably wanted to make a vector of size "size" containing only 1s? To achieve this, use an expression e.g. x1'range => '1' where x1 can be a vector variable of which size is size.
You use + operator for bit_vector type which is not defined. You probably intended to use std_logic_vector type because you imported ieee.std_logic_unsigned.all. Alternatively use numeric_bit_unsigned package.
Btw. this package is not supported so you might want to change the data type with a conversion to unsigned and use ieee.numeric_std.all package instead.
There might be errors about undeclared types etc. Check how you use the use statements.
There are other small syntax errors as well (and some logic errors, I think) but you should be able to solve them after these fixes by reading the error messages.