No warning concerning port and assignment in Questa 10.7b

Question

I have a simple code:

module test (
  input a, 
  output b
  );    

  assign a=0;
  assign b=0;

endmodule 

As you can see a is input, which assigned, thats wrong.. but no warning is shown; my script for compile.do:

set work work
vlib -type directory $work

vlog -work $work +acc    ../src/test.sv +incdir+../inc

and sim.do:

set work work
vlib -type directory $work
vlog -work $work +acc    ../src/test.sv +incdir+../inc

How can I see the warning? In case I do assign a=b; (also error should be since b is output) also no error, just a is h'x;

Answer 1

You must be coming from VHDL. 😏 This is specifically allowed by Verilog when dealing with nets (which you have implicitly specified)

Section 23.3.3.1 Port coercion of the IEEE 1800-2017 LRM
A port that is declared as input (output) but used as an output (input) or inout may be coerced to inout.

SystemVerilog can enforce port direction when using variables instead of nets because only there can only be one continuous driver to a variable. However, there is nothing from preventing you from reading the value of a module output from within the module.