Looping in vhdl

Question

I am writing a code for RSA algorithm . I need to use loop for it to work. But the loop doesn't have definite bound. So it is not sythesizable . Is there any other methods for looping? Please help.

Answer 1

The kind of loop is irrelevant. You cannot synthesise a variable amount of hardware. However, for a loop to be synthesisable, it must have a definite upper bound - a maximum number of iterations must be clear to the synthesiser. It is allowed to exit a loop early.

I would recommend you stick to for loops for synthesis. This will make your code more portable.