I have the following code:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity read_fail is
end entity read_fail;
architecture test of read_fail is
begin
process
variable l : line;
constant s : string(2 to 5) := "1111";
variable a : std_logic_vector( 3 downto 0);
begin
l := new string'(s);
read(l, a);
DEALLOCATE(l);
report "done read";
wait;
end process;
end architecture;
and when run in ActiveHDL, I get the following error:
RUNTIME: Fatal Error: RUNTIME_0047 std_logic_1164-body.vhdl (1114): Index 1 out of range (2 to 5)
Now, I can see why this is happening, but I'm not sure if this is an LRM failure, or if Aldec have their own implementation? There is nothing (I can find) in the LRM that specifies that the line has to start from index 1.
If I change a to be a bit_vector, there is no problem (as I assume the string is aliased inside the read procedure, or 'range is used).
If there is an LRM/library issue, it would be nice to have it fixed in VHDL 2018/19.
So this appears to be an Aldec issue, a work-around is to renumber returned slices:
procedure renumber (l : inout line) is
variable tmp : line;
begin
tmp := new string(1 to l'length);
tmp.all := l.all;
DEALLOCATE(l);
l := tmp;
end procedure;
Definitely the IEEE std_logic_1164 package body is not defined by Aldec but still distributed by IEEE. Please simply switch off the acceleration for this package in other simulators to get the same results as Aldec does.