how to control rounding mode of real number in systemverilog

Question

I would like to write a test for FPU module and can't find out a way to change a rounding mode of real numbers in SystemVerilog. Does the system function or any easy method exist to do that?

Thank you in advanced

Answer 1

There's no way to change the rounding mode (away from 0). You can choose to truncate using the $rtoi function, or look at the bit patterns directly using $realtobits.