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chisel

Chisel3: How to create a register without reset signal in RawModule?

I want to create a RegNext in a RawModule, with the help of withClock. However, it can't work while the error information shows that missing implicit reset. So I have to write it like this:

class Test extends RawModule {
  ...
  val nothing = Wire(Bool())
  nothing := DontCare
  val a = withClockAndReset(io.ui_clk, nothing) {
    RegNext(~io.in)
  }
  ...
}

Is there any better solution?

Solution

  • You can shorten it a little bit by using

    withClockAndReset(io.ui_clk, false.B)

    but I can't figure out a way to do it otherwise. withClock uses withClockAndReset internally and that's what cases the error. Maybe someone else has a better answer.