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vhdl

Why am I getting errors in lines 56-61?


I am trying to set up a problem for state machines in lab and I keep receiving errors when trying to compile in Quartus

I have tried using commas, else statements and nothing seems to work

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.All;

ENTITY SM_VHDL IS  -- Do not modify this entity statement!
  PORT(X       : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       RESETN,
       CLOCK   : IN  STD_LOGIC;
       Z       : OUT STD_LOGIC;
       Q       : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)  );
END SM_VHDL;       -- Do not modify this entity statement!


ARCHITECTURE behavior of SM_VHDL IS
  TYPE STATE_TYPE IS (A, B, C);
  SIGNAL state : STATE_TYPE;

BEGIN
    PROCESS(CLOCK, RESETN)
      BEGIN
        IF RESETN = '0' THEN
          state <= A;
        ELSIF CLOCK'EVENT AND CLOCK = '1' THEN
          CASE state IS
            WHEN A =>
              CASE X IS
                WHEN "00"   =>
                                        state <= B;
                                WHEN "11"   =>
                                        state <= C;
                                WHEN OTHERS =>
                                        state <= A;
              END CASE;
            WHEN B =>
              CASE X IS
                WHEN "10"   =>
                                        state <= A;
                                WHEN "11"   =>
                                        state <= C;
                                WHEN OTHERS =>
                                        state <= B;
              END CASE;
            WHEN C =>
              CASE X IS
                WHEN "00"   =>
                                        state <= B;
                                WHEN "01"   =>
                                        state <= A;
                                WHEN OTHERS =>
                                        state <= C;
              END CASE;
          END CASE;
        END IF;
      END PROCESS;

    Z  <= '1' WHEN C;
                  '0' WHEN A;
                  '0' WHEN B;

    Q  <= "00" WHEN A;
                  "01" WHEN B;
                  "10" WHEN C;
                  "11" WHEN "-";

END behavior;

I need it to compile


Solution

  • The syntax for assigning to Z and Q is wrong for multiple issues:

    • Missing WITH state SELECT ... before assign
    • Uses ";" between when parts, use , instead
    • Cant use "-" (don't care) after last when, use OTHERS instead

    So updated code:

    WITH state SELECT Z <=
          '1' WHEN C,
          '0' WHEN A,
          '0' WHEN B;
    
    WITH state SELECT Q <=
          "00" WHEN A,
          "01" WHEN B,
          "10" WHEN C,
          "11" WHEN OTHERS;
    

    Btw. consider using ModelSim Starter Edition as compiler/simulator before moving to Quartus, since the compile time is faster and messages often better.