How to fix [ near "then": (vcom-1576) expecting == or '+' or '-' or '&' ] error?

Question

I am getting 3 same errors after compiling this code -

** Error: C:/Modeltech_pe_edu_10.4a/examples/DECODER.vhd(24): near "then": (vcom-1576) expecting == or '+' or '-' or '&'.

I have tried adding "end if;" at the end but it gives me the above errors and the following error -

** Error: C:/Modeltech_pe_edu_10.4a/examples/DECODER.vhd(35): VHDL Compiler exiting

library IEEE;

use IEEE.std_logic_1164.all;

entity DECODER is
port
(
I0: in std_logic;
I1: in std_logic;
D0: out std_logic;
D1: out std_logic;
D2: out std_logic;
D3: out std_logic
);
end DECODER;

architecture bhv of DECODER is
begin
process(I0,I1) is
begin
if (I0='0' AND I1='0') then 
  D0<= (NOT I0) AND (NOT I1);

elseif (I0='0' AND I1='1') then 
  D1<= (NOT I0) AND I1;

elseif (I0='1' AND I1='0') then 
  D2<= I0 AND (NOT I1);

elseif (I0='1' AND I1='1') then 
  D3<= I0 AND I1;
end process;
end bhv;

Answer 1

There are two syntax errors.

Change elseif to elsif.

Add final end if just before end process.

Functionally to the code is odd; if synthesized it will infer latches since the output assigned is dependent on the input value, and the condition for doing an assign at each branch of the if is the same as the value assigned, thus the assigned value '1', so the process is equivalent to:

process (I0, I1) is
begin
  if (I0 = '0' and I1 = '0') then
    D0 <= '1';
  elsif (I0 = '0' and I1 = '1') then
    D1 <= '1';
  elsif (I0 = '1' and I1 = '0') then
    D2 <= '1';
  elsif (I0 = '1' and I1 = '1') then
    D3 <= '1';
  end if;
end process;

With no initial or reset value for the outputs, it appears that the code will not perform any meaningful operation.