I was a bit nervous about the synthsizability of certain VHDL features, so I thought it might be a good idea to see what is written in the standard (IEEE 1076.6 "IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis").
To my astonishment, I found that there is no current standard: the 1999 version has been superseded by the 2004 version; the 2004 version has the status "withdrawn":
https://standards.ieee.org/standard/1076_6-2004.html
I find it hard to believe that there is no need for a standard subset, so I hope someone can explain why the appears to be no current standard.
First DASC made them joint standards with IEC. When this happened, the numbers changed - which made them hard to find.
Some time later, both the VHDL and Verilog standards were retired by DASC (Design Automation Standards Comittee) because no one stepped forward to maintain them. Since I do not generally attend DASC meetings, I missed that this happened.
I worked on the VHDL RTL standard. It lacks reward when you put forward coding styles and attributes and vendors such as Xilinx and Altera do not implement them.
It can be revived. It is worth reviving if you can get the tool vendors (Xilinx, Altera, Synopsys, Mentor, and Cadence) participating and implementing the standard.
However, without them participating and committing to implement new features, then the effort by a user led committee would not be worth the time.
If you think of just the statemachine and ROM/RAM attributes, we really need some consistency out of industry - the current state is embarrassing.