VHDL Quartus Does Not Recognize "+" and "-"

Question

So i have tried to make a program that performs either addition or substractions following a simple condition but my VHDL compiler keeps telling me that it can't recognize what "+" and "-" are for. I'm also not sure about the library i'm using.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY ADDSUBS IS
PORT( CNTRL: in std_logic;
      NUM1, NUM2: in std_logic_vector(7 downto 0);
      SUM: out std_logic_vector(8 downto 0));
END ADDSUBS;

ARCHITECTURE A4 OF ADDSUBS IS
BEGIN
SUM <= ('0' & NUM1) + ('0' & NUM2) WHEN (CNTRL='0') ELSE
       ('0' & NUM1) - ('0' & NUM2) WHEN (CNTRL='1');
END;

Answer 1

You havent included any packages that can do arithmatic with std_logic_vectors. ('0' & NUM1) is still a std_logic_vector, you need to cast it to an unsigned/signed:

unsigned('0' & NUM1)