verilog code is working in isim(xilinx 14.2) but is not working onspartan6

Question

i have written a simple counter code in verilog (xilix 14.2). The code is working properly in the isim but i am not able to dump it onto spartan6. When I try to do dump the code, a red light is ON , on the spartan 6 and the code is not dumped . Please let me know the changes i need to make.

module clk(int_clk,ext_pulse,reset,pos_count,neg_count);
input int_clk;
input ext_pulse;
input reset;
output reg [7:0] pos_count;
output reg [7:0] neg_count;
reg [7:0] count;
always@(posedge int_clk)
if(reset)
begin
pos_count<=0;
neg_count<=0;
end
else if(ext_pulse)
begin
neg_count<=neg_count+1;
pos_count<=0;
end
else
begin
pos_count<=pos_count+1;
neg_count<=0;
end
endmodule

Answer 1

Hey you haven't put a begin..end in the always block. Moreover you have used a synchronous reset which is generally not advisable. I made some changes to your code. By the way did you generate the bitstream?

module clk(int_clk,ext_pulse,reset,pos_count,neg_count);
input int_clk;
input ext_pulse;
input reset;

output reg [7:0] pos_count;
output reg [7:0] neg_count;
reg [7:0] count;              //This reg is unused

always@(posedge int_clk or posedge reset) //I am assuming you want active high reset
begin
if(reset)
begin
  pos_count<=0;
  neg_count<=0;
end
else if(ext_pulse)
begin
 neg_count<=neg_count+1;
 pos_count<=0;
end
else
begin
 pos_count<=pos_count+1;
 neg_count<=0;
end
end
endmodule