Which is the synthesized digital circuit for this [verilog] mux with an uncompleted sensibility list?

Question

Which is the synthesized not optimized digital circuit for the following code:

a, b and c are 1 bit long. sel has 2 bits.

always@(a, b, sel)
case(sel)
    begin
    2'b00: a;
    2'b01: b;
    2'b10: c;
    default: 0;
    end
endcase

If i am not mistaken we would have a mux with three inputs and two selection bits.

As selection bits we have sel[0] and sel[1]. As inputs we have a, b and a latch. The latch will have as input c and something else. I dont know what else has to enter the latch.

This question is just educational.

Answer 1

Most synthesizers do not consider the sensitivity list unless it is for synchronous logic. The latching behavior you would see in simulation will not happen post-synthesis. The major reason @* was added in IEEE1364-2001 prevent accidental omissions from sensitivity list.

If you truly want to output a latched version of c, then you need to create the latch before the mux:

always @*
  if (lat_en) c_latch <= c;
always @*
  case(sel)
    2'b00: a;
    2'b01: b;
    2'b10: c_latch;
    default: 0;
  endcase

Level-sensitive latches are not common on FPGAs. The are used sparingly on ASICs due to timing concerns. Edge-sensitive flip-flops are generally preferred:

always @(posedge clk)
  if (update) c_ff <= c;
always @*
  case(sel)
    2'b00: a;
    2'b01: b;
    2'b10: c_ff;
    default: 0;
  endcase