uninitialized out port y(3 downto 0) has no driver. # This port will contribute value (UUUU) to the signal network

Question

Barrel.vhd file

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Barrel is

port (w :in std_logic_vector(3 downto 0);
      s:in std_logic_vector (1 downto 0);
      y:out std_logic_vector (3 downto 0)
);
end Barrel;

architecture Barrel_A of Barrel is
begin

with s select
y(3 downto 0) <= w(3 downto 0) when "00",
     w(0) & w(3 downto 1)when "01",
     w(1 downto 0)& w(3 downto 2) when "10",
     w(2 downto 0)& w(3) when "11",
     w  when others;
end architecture Barrel_A; 


 Test Bench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity Barrel is
port (y:        out std_logic_vector(3 downto 0);
      w:        in  std_logic_vector(3 downto 0);
      s:        in  std_logic_vector(1 downto 0));

end Barrel;


architecture Barrel_A of Barrel is

component Barrel
port (y:        out std_logic_vector(3 downto 0);
      w:        in  std_logic_vector(3 downto 0);
      s:        in  std_logic_vector(1 downto 0));
end component;


signal w1 : std_logic_vector(3 downto 0) := (others =>'0');
signal y1 : std_logic_vector(3 downto 0); 
signal s1 : std_logic_vector(1 downto 0) := (others =>'0');

begin
  dev_to_test:  Barrel 
        port map(y => y1,w =>w1,s => s1); 



    z:  process
    begin
        w1 <="0010";
        wait for 100 ns;
    end process z;


k :process
variable count : signed(1 downto 0) :=(others => '0');
begin

s1 <= std_logic_vector(count);
 --for i in 0 to 1 loop
for k in 0 to 3 loop
wait for 100 ns;
count := count +1;
s1 <= std_logic_vector(count);
end loop;
end process k;
end architecture Barrel_A;

Error:

Error :uninitialized out port /barre  y(3 downto 0) has no driver. # This port will contribute value (UUUU) to the signal network.  

How to resolve this error. Please help me

Answer 1

Your testbench and UUT are both called "Barrrel" I get the feeling the test bench is instantiating itself recursively.