In the rocket core bypass logic
val bypass_sources = IndexedSeq(
(Bool(true), UInt(0), UInt(0)), // treat reading x0 as a bypass
(ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata),
(mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata),
(mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data))
What do ex_ctrl.wxd and mem_ctrl.wxd stand for?
As I understand it, wxd is set for an instruction that writes a value to a register, i.e. has a result value, so writes to the register file. Some reasonably simple decode logic (e.g. test for R-type instruction) identifies whether each instruction is such a writer or not.
Also as I understand it, ex_ctrl and mem_ctrl refer to instructions in their pipeline stages, ex, and mem, respectively — so ex_ctrl.wxd is set when the instruction in the ex stage is one that writes to a register (even though it won't do the write until the wb stage).
Background
The rocket micro architecture suspends reading coprocessor results — as reading coprocessor results means writing a processor register, so also a write to the processor's register file — when wxd is asserted for instructions in the wb pipeline stage, giving processor instructions priority over coprocessor instructions. A coprocessor result value is only transferred into the processor register file when wxd is set false (meaning the processor instruction won't write).
This mechanism limits the number of ports needed to write the register file.