What is the advantage of using a testbench rather than a ".do" file in ModelSim?
A ".do" file allows me to force and examine ports. The testbench seems to do exactly the same thing. So why use a testbench and not a ".do" file?
Thank you!
Forcing ports is a very simplistic method of driving a design. Its main purpose is to override what is already generated in HDL (like fault injection) but can be used to drive a UUT.
The problem using force is that you can only provide very simplistic test cases. When you need to start writing self checking testbenches, BFMs (bus functional models), randomisation, coverage, then Force from TCL is not going to be much use.
For example - you have some interface that has a some behaviour to write a byte of data. I know I would rather write the HDL :
send_byte(x"AB", some_if);
rather than
force some_if 0 10ns, 1 20 ns, 0 30ns ....... etc
The procedure call has more meaning to another reader, and can easily be reused to send many bytes and in many tests.