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cachingassemblyarmcpu-cachememory-barriers

Cache, Branch predictor and TLB maintenance operations

About ARM DSB memory barrier instruction:

DSB -

Data Synchronization Barrier acts as a special kind of memory barrier. No instruction in program order after this instruction executes until this instruction completes.

Well understood, Next:

This instruction completes when:

All explicit memory accesses before this instruction complete.

All Cache, Branch predictor and TLB maintenance operations before this instruction complete.

Wait, what exactly is cache, branch predictor and TLB maintenance means? Does it means flushing? and does it means that the DSB instruction itself can trigger such flushing? and what else is considered as maintenance?

Solution

  • I think this is an issue of English grammar ambiguity. I think they mean

    • cache operation (all side-effects of loads/stores, or explicit flush / invalidate after an MMU operation)
    • branch predictor operation (e.g. globally enable/disable branch prediction)
    • TLB-maintenance operation (e.g. invalidate a TLB entry after changing a page table entry)

    I don't think they're trying to describe branch-predictor operations as "maintenance", and the word "maintenance" is only supposed to go with "TLB" in that sentence.

    (Some branch-predictor operations could maybe be described as maintenance, if ARM has added branch-predictor flush operations for Spectre mitigation, the way Intel has for their x86 CPUs with their recent microcode updates that added a new model-specific register. (https://access.redhat.com/articles/3311301). But I don't think that's what their sentence is trying to say here.)