Makefile object file generation, variable substitution, and other questions

I'm currently trying to create a Makefile for a c university project, but reading through the tutorials hasn't quite helped me (also, the makefile is not part of the evaluation process, and we aren't taught how to do it)

My objective is making the makefile automatic, so it automatically creates object files from .c files in src (src/*.c), puts the object files in the bin folder, and links them into an executable in the main directory.

project/
    bin/
        (object files)
    src/
        (source files)
    executable
    Makefile

So far, I've roughly put together this makefile and test source code, but it doesn't work the way I intend it to, which I'll explain how just ahead:

#compiler used
COMPILER = gcc

#flags for individual object file compilation
FLAGS = -Wall -ansi -g
#RELEASE
# -Wall -ansi -O3
#DEVELOPMENT
# -Wall -ansi -g

#source .c files
SOURCE = $(wildcard src/*.c)
#object files created
OBJECTS = $(SOURCE:.c=.o)
OBJECTS = $(SOURCE: src/=bin/)

#executable name
EXECUTABLE = app

############################################################

all: $(EXECUTABLE)

$(EXECUTABLE): $(OBJECTS)
    $(COMPILER) $(FLAGS) -o $(EXECUTABLE) $(OBJECTS)

%.o: %.c
    $(COMPILER) $(FLAGS) -c %< -o %@

The result is the following command:

user@user-lenovo:~/Desktop/C Projects/AED/project$ make
gcc -Wall -ansi -g -o app src/main.c src/test.c

Ironically, it works, but really shouldn't. It also defeats the purpose of having a makefile, as everything is compiled again once one change is detected.

First of all, what I noticed is OBJECTS directly copied SOURCE, and didn't substitute .c for .o, or src/ for bin/. I've tried substituting the '=' for ':=' but the result is the same, and I don't quite understand what the difference between them is in the first place. My idea would be src/main.c becoming bin/main.o, for example.

%.o: %.c
    $(COMPILER) $(FLAGS) -c %< -o %@

This part is my also failed attempt at generating all the object files individually with a single target. I tried reading up on it, but couldn't figure out how these work: '%<', '%@' or the '%.o' and '%.c'

I do believe it isn't being run at all though, since no object files showed up.

I hope you can help me fix this mess up, thanks in advance!

Solution

OBJECTS = $(SOURCE:.c=.o)
OBJECTS = $(SOURCE: src/=bin/)

You're assigning to OBJECTS twice there - the first result gets overwritten by the second which doesn't work. You want to combine them into one statement like this

OBJECTS=$(SOURCE:src/%.c=bin/%.o)

Your next problem is you need to tell make that "bin/whatever.o" is built from "src/whatever.c". Currently it'll look for "whatever.c" in "bin/"

So your recipe for building .o files needs the directories added

bin/%.o: src/%.c
    $(COMPILER) $(FLAGS) -c $< -o $@

You also should have $@ instead of %@ and $< instead of %<