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Difference between process and "vanilla" VHDL

I'm practicing VHDL, and I have a fundamental question about "simple" statements which do not require a process.

I would like to know the difference between

c <= a and b;

Where the statement is not inside a process, just written after the architecture begin, and

process(a,b)
begin
    c <= a and b;
end process;

Will these results produce the same thing? Ty :)

Solution

  • Yes, the two descriptions are equivalent.

    The concurrent signal assignment c <= a and b is evaluated at each update of any of the argument (a or b), and the process will also evaluate each time any of the arguments in the sensitivity list is updated (a or b).

    In the simple example it not required to use a process, but for more complex expressions, the process has the advantage that control structures like if and for can be used, which is not directly possible in a concurrent signal assignment. Also, for sequential logic a process is required.