I have this small mismatch in my code vhdl code. I'm doing a signal stretcher using a clock counter. Basically i reiceve an external signal as "start" , after i synchronize it with with a 2 ff synchronizer and use this "syncrhro-start" for my fsm. It read the value in a register and let the "gate" open for the numer of count that i set to the reg. My clock has a period of 25 ns ( 40MHz clock). So when i set the value "0" on the register, i don't have any signal (as expected). If i set "1" i have a signal of 50 ns instead of 25ns. If i set "2" i have a a 75ns signal-out. Conceptually it is working (2, in binary are 01, so it start to count from 0, so 0-1-2 are 3 clock run/75ns).
But i need to have with "1" a 25ns signal, with 2 a 50ns and so on.
Here my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity gate is
Port (
start : in STD_LOGIC := '0'; --segnale di start
clk : in STD_LOGIC; --clock di ingresso
reset : in STD_LOGIC; --ff reset
gate: out STD_LOGIC; --gate in uscita
lenght: in std_logic_vector (7 downto 0)
);
end gate;
architecture behavioral of gate is
--type state_type is (idle, gate_up, final);
type state_type is (idle, stretching);
signal state : state_type;
begin
process (reset, clk, start)
variable index : integer :=0;
variable gate_v: std_logic;
variable gatelen : integer;
begin
gatelen := to_integer(unsigned(lenght));
if reset = '1' then
gate_v := '0';
index := 0;
else
if rising_edge(clk) then
case state is
when idle =>
index := 0;
gate_v :='0';
if(start = '1') then
state <= stretching;
else
state <= idle;
end if;
when stretching =>
if index = gatelen then
state <=idle;
else
gate_v := '1';
index := index + 1;
state <= stretching;
end if;
when others => null;
end case;
end if;
end if;
gate <= gate_v;
end process;
end Behavioral;
I can partially fix things withi this mod
gatelen := to_integer(unsigned(lenght))-1;
but in this case, if i put "1" on the registry, i will not have any signal, and if i put "2" i have a output signal of 50ns. The 25ns output signal is still missing.
Any help will be greatly appreciate!
Edit:
Thanks for the Reply, as requested, i will also add the code of my test bench.
library ieee;
use ieee.std_logic_1164.all;
entity gate_tb is
end gate_tb;
architecture behavioral of gate_tb is
signal master_clk : std_logic := '0';
signal global_rst : std_logic := '0';
signal gate_on : std_logic := '0';
signal gate_out : std_logic := '0';
constant clk_period : time := 25 ns; --40ns
signal lenght_tb : std_logic_vector (7 downto 0);
component gate is
port(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
gate: out std_logic;
lenght: in std_logic_vector ( 7 downto 0)
);
end component gate;
begin
uut : gate port map (
clk => master_clk,
reset => global_rst,
start => gate_on,
gate => gate_out,
lenght => lenght_tb
);
gate_process : process
begin
master_clk <= '0';
wait for clk_period/2; --for 10 ns signal is '0'.
master_clk <= '1';
wait for clk_period/2; --for next 10 ns signal is '1'.
end process;
--stimulus
stim : process
begin
lenght_tb <= "00000001";
wait for 50 ns;
global_rst <= '1';
wait for 30 ns;
global_rst <= '0';
wait for 50 ns;
gate_on <= '1';
wait for 35 ns;
gate_on <= '0';
wait for 150 ns;
gate_on <= '1';
wait for 35 ns;
gate_on <= '0';
wait for 150 ns;
gate_on <= '1';
wait for 35 ns;
gate_on <= '0';
wait for 150 ns;
gate_on <= '1';
wait for 35 ns;
gate_on <= '0';
wait for 150 ns;
end process;
end behavioral;
So if in this TB i set lenght_tb <= "00000000"; the out is 0 is i set lenght_tb <= "00000001"; the out is a signal of 50 ns and not 25 ns.
The problem is in the state stretching, look for example for reg=1:
You have to set gate=0 when you check if index = gatelen:
when stretching =>
if index = gatelen then
gate_v := '0';
state <=idle;
else
gate_v := '1';
index := index + 1;
state <= stretching;
end if;