how to assign a vector in vhdl to zero?

i have a vector temp in vhdl and i want the vector to be equal to zero if the vector reached the maximum count_limit .. the vector size is generic .. how can i do something like this ?

GENERIC ( SIZE      : INTEGER := 8);
constant count_limit : std_logic_vector(SIZE - 1 downto 0) := ( others => '1'); -- max value 
signal temp: std_logic_vector(SIZE - 1 downto 0);

-- here i want to check if temp was equal to the max vaue then i want temp to be zero
-- here is what i did but thats not correct !

temp <= ( others => '0');

Solution

To me it seems like what you want to do is this:

--inside declaration part of the architecture
signal temp : unsigned(SIZE-1 downto 0);
constant count_limit : unsigned(SIZE - 1 downto 0) := ( others => '1');

--in the body
clocked_count: process(clk) begin
  if rising_edge(clk) then
    if temp < count_limit then
      temp <= temp +1;
    else temp <= (others => '0');
    end if;
   end if;
 end

The above process will increment temp's value every clock cycle as long as it's saved(last) value is smaller than count_limit. When count_limit is reached, temp is zeroed. The comparisons work only if you declare the signals as unsigned because then there is no ambiguity about what the bit vector represents.