How to wait for a signal to be assigned new value within a process without using wait statement in vhdl

Question

Basically I have to code a university project in vhdl. The main issues is that during a process I need assign a std_logic signal a '1' value so that a secondary process can start. I'm aware that the assignment to a signal is at the next clock cycle. But the problem is that I need to create a synthesizable hardware component so i can't really use wait statements. So here is the question: how can I wait a cycle of clock without using wait statements?

Answer 1

You need to use clocked process with a structure as follows. Process_2 will start on the clock cycle after start_signal is set.

process_1 : process(clock)
begin
  if rising_edge(clock) then
    start_signal <= '1';
  end if;
end process;

process_2 : process(clock)
begin
  if rising_edge(clock) then
    if start_signal then
      --do stuff
    end if;
  end if;
end process;