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vhdlsimulationfpgaxilinxvivado

Undefined type in block design when using custom IP

I am busy getting some hands on experience using Xilinx Vivado.

Taking a VHDL sine generator from github (https://github.com/jorisvr/vhdl_sincos_gen) I made an IP package out of it. I defined the ports: enter image description here

So the 'in_phase' port is of type unsigned.

After packaging the IP I created a new project with a block design and instantiated the IP:

enter image description here

This works and I can synthesize the design. Simulation however fails. I get the following errors in the elaboration log:

Starting static elaboration
ERROR: [VRFC 10-619] entity port in_phase does not match with type std_logic_vector of component port [/home/dinne/Xilinx/projects/nexys4ddr_tst/nexys4ddr_tst.ip_user_files/bd/design_1/ip/design_1_sincos_gen_0_0/sim/design_1_sincos_gen_0_0.vhd:80]
ERROR: [VRFC 10-619] entity port out_sin does not match with type std_logic_vector of component port [/home/dinne/Xilinx/projects/nexys4ddr_tst/nexys4ddr_tst.ip_user_files/bd/design_1/ip/design_1_sincos_gen_0_0/sim/design_1_sincos_gen_0_0.vhd:81]
ERROR: [VRFC 10-619] entity port out_cos does not match with type std_logic_vector of component port [/home/dinne/Xilinx/projects/nexys4ddr_tst/nexys4ddr_tst.ip_user_files/bd/design_1/ip/design_1_sincos_gen_0_0/sim/design_1_sincos_gen_0_0.vhd:82]

Somehow the port types are changed. If I check the port properties of for example the "in_phase" port I see that the type is "undef". enter image description here

Also If I check the generated IP wrapper code I see that the port types have changed. Again the 'in_phase' port should be unsigned, but is "std_logic_vector".

enter image description here

How to fix the IP port types and get the simulation to run?

Solution

  • Vivado only allows ports of types std_logic or std_logic_vector for custom IPs. Details can be found here. Under the section Top-Level HDL Requirements, on Page 12 in this document they clearly mention:

    Regardless of the top-level port type, when you synthesize the IP out-of-context (OOC), the resulting IP netlist ports are converted to std_logic or std_logic_vector. The converted netlist ports could cause type mismatch issues with RTL simulation. For Verilog, module declarations with complex or split ports are not supported.

    And in the same document, on page 63, under the section Ports and Interfaces:

    ° Type Name: The port type (std_logic or std_logic_vector).

    As each custom-IP is considered as a top level entity, using unsigned type in the top port is unfortunately not supported.