I wrote a VHDL function vectorize() to convert an array of std_logic_vector (slv_1d_array_type type in my code) to std_logic_vector.
Vivado 2018.2 generates this error [Synth 8-5882] found unsupported attribute ["test_top.vhd":41] with the example below. I have configured Vivado to use VHDL-2008.
How can I make these 'length attributes work to avoid passing array size along ?
-- Libraries
------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------------------------------------------------
entity test_top is
generic(
DATA_WIDTH : positive := 32
);
port(
O_DATA : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity test_top;
------------------------------------------------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------------------------------------------------
architecture rtl of test_top is
--------------------------------------------------------------------------------------------------------------------
-- Types definition
--------------------------------------------------------------------------------------------------------------------
type slv_1d_array_type is array (natural range <>) of std_logic_vector; -- One-dimensional std_logic_vector array type.
--------------------------------------------------------------------------------------------------------------------
-- Functions declaration
--------------------------------------------------------------------------------------------------------------------
function vectorize(constant SLV_1D_ARRAY : in slv_1d_array_type) return std_logic_vector is
variable vector_v : std_logic_vector(SLV_1D_ARRAY'length * SLV_1D_ARRAY'element'length - 1 downto 0);
begin
for i in SLV_1D_ARRAY'range loop
vector_v(SLV_1D_ARRAY'element'length * (i + 1) - 1 downto SLV_1D_ARRAY'element'length * i) := SLV_1D_ARRAY(i);
end loop;
return vector_v;
end function vectorize;
--------------------------------------------------------------------------------------------------------------------
-- Signals declaration
--------------------------------------------------------------------------------------------------------------------
signal data_r : slv_1d_array_type(0 to DATA_WIDTH / 8 - 1)(7 downto 0) := (others => (others => '0'));
begin
O_DATA <= vectorize(data_r);
end architecture rtl;
According to UG901 at chapter 6 "VHDL-2008 Language Support" there is no mention of 'element attribute. So it is not officially supported.
This thread from Xilinx forums states that it was badly supported and has been removed starting from Vivado 2016.3.
However, the code example above is accepted by ModelSim 10.6c.
The work around provided by @Juergen is working as expected with Vivado 2018.2. Here is an updated version of the example including the work around:
-- Libraries
------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------------------------------------------------
entity test_top is
generic(
DATA_WIDTH : positive := 32
);
port(
O_DATA : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity test_top;
------------------------------------------------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------------------------------------------------
architecture rtl of test_top is
--------------------------------------------------------------------------------------------------------------------
-- Types definition
--------------------------------------------------------------------------------------------------------------------
type slv_1d_array_type is array (natural range <>) of std_logic_vector; -- One-dimensional std_logic_vector array type.
--------------------------------------------------------------------------------------------------------------------
-- Functions declaration
--------------------------------------------------------------------------------------------------------------------
function vectorize(constant SLV_1D_ARRAY : in slv_1d_array_type) return std_logic_vector is
variable vector_v : std_logic_vector(SLV_1D_ARRAY'length * SLV_1D_ARRAY(SLV_1D_ARRAY'low)'length - 1 downto 0);
begin
for i in SLV_1D_ARRAY'range loop
vector_v(SLV_1D_ARRAY(SLV_1D_ARRAY'low)'length * (i + 1) - 1 downto SLV_1D_ARRAY(SLV_1D_ARRAY'low)'length * i) := SLV_1D_ARRAY(i);
end loop;
return vector_v;
end function vectorize;
--------------------------------------------------------------------------------------------------------------------
-- Signals declaration
--------------------------------------------------------------------------------------------------------------------
signal data_r : slv_1d_array_type(0 to DATA_WIDTH / 8 - 1)(7 downto 0) := (others => (others => '0'));
begin
O_DATA <= vectorize(data_r);
end architecture rtl;