I am using Lattice Diamond and I have a verilog file with a bunch of `define statements to define global constants.
I include this "header" file into another file. It finds the file but there is an error:
" 2049990 ERROR - C:/_libraries/LatticeDiamond/verilog-uart/source/uart/uart_loopback_tb.v(184,38-184,53) (VERI-1128) UART_1_STOP_BIT is not declared "
I have the directory of the header file set as an include path in the project settings for the implementation as well.
/********************************************************************************************
* @file UART_Header.v
* @brief
* Defines UART module parameter constants
*
* @details
* This file is to support the UART_core.v
*
*
* @namespace UART_
********************************************************************************************/
`ifndef UART_HEADER_FILE
`define UART_HEADER_FILE
// UART core register addresses
`define UART_WRITE_ADDR = 8'h00; ///< UART TX address
`define UART_READ_ADDR = 8'h00; ///< UART address to read received data
`define UART_LCR_ADDR = 8'h03; ///< Line control register
`define UART_LSR_ADDR = 8'h05; ///< Line status register
`define UART_DIV_LW_ADDR = 8'b00000111; ///< Baud Rate divisor register low word
`define UART_DIV_HW_ADDR = 8'b00000110; ///< Baud Rate divisor register high word
// UART core bit masks
`define UART_5_DATA_BITS = 16'b00000000; ///< 5 data bits mask
`define UART_6_DATA_BITS = 16'b00000001; ///< 6 data bits mask
`define UART_7_DATA_BITS = 16'b00000010; ///< 7 data bits mask
`define UART_8_DATA_BITS = 16'b00000011; ///< 8 data bits mask
`define UART_1_STOP_BIT = 16'b00000000; ///< 1 stop bit mask
`define UART_1_5_STOP_BIT = 16'b00000100; ///< 1.5 stop bits mask
`define UART_2_STOP_BIT = 16'b00001000; ///< 2 stop bits mask
`define UART_PARITY_ENABLE = 16'b00010000; ///< Enable parity bit mask
`define UART_PARITY_DISABLE = 16'b00000000; ///< Disable parity bit mask
`endif
//EOF
Then I have a file that includes that file like so.
`ifndef UART_LOOPBACK_TB_FILE
`define UART_LOOPBACK_TB_FILE
//*******************************************************************************************
// Includes
//*******************************************************************************************
`include "source/uart/UART_header.v"
// Rest of the code for this file
.....................
UL_TB_WriteReg((UART_8_DATA_BITS | UART_1_STOP_BIT | UART_PARITY_DISABLE), UART_LCR_ADDR);
...................
`endif
Why can't it find my `defines? The file that includes the header file is even in the same directory as the header file itself. Does Lattice Diamond support this?
I also tried `include "UART_header.v" since it's in the same directory, but that gives the same error.
Surely you mean this:
UL_TB_WriteReg((`UART_8_DATA_BITS | `UART_1_STOP_BIT | `UART_PARITY_DISABLE), `UART_LCR_ADDR);
// ^ ^ ^ ^
Things that have been defined in Verilog need to be preceded by a back quote.