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vhdl

Process doesn't work due simulation

I wrote this code to understand process in vhdl but strangely I saw the simulation that doesn't work properly my code : 

entity test is
    port(
        i1 : in std_logic;
        i2 : in std_logic;
        r : out std_logic
    );
end test;

architecture Behavioral of test is
signal g : std_logic;
begin
    process(i1)
        begin
        if i1 = '1' then 
            g <= '1';
        else 
            g <= '0';
        end if;
    end process;
    process(i2)
    begin
        if i2 = '1' and g = '0' then
            r <= '1';
        else
            r <= '0';
        end if;
    end process;

end Behavioral;

and this is my result : enter image description here

when i process i1 so g should be 1 in the first period so r should be 0 but r is 1 after i2 is 1

Solution

  • Your are using g in the second process but it is not in the process sensitivity list. 

    process(i2,g)
begin
    if i2 = '1' and g = '0' then
...