output is not connected to the rest of the design in rtl

Question

This is my first time using rtl so I am having some issues which may be simple, but I have not been able to find anything that explains why this is happening and how to fix it. Currently when I create an rtl from my vhdl code, the ouputs are not shown to be connected to the rest of the design. The image below shows the outputs, not the rest of the design since it is pretty big.

The parts of my code which are relevant can be seen below:

`library IEEE;

 use IEEE.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 use ieee.numeric_std.all;

 entity FIFOClockOut is
port (
    --Inputs
    dataIn      :   IN  std_logic_vector(7 downto 0);       -- data input
    clk         :   IN  std_logic;                          -- clock input
    EnableWr    :   IN  std_logic;                          -- a value is being transmitted to the FIFO
    clearMem    :   IN  std_logic;                          -- clears the memory of the FIFO
    resetOut    :   IN  std_logic;                          -- resets the FIFO output counter
    resetFull   :   IN  std_logic;                          -- resets the the FIFO completely
    --Outputs
MemNear     :   INOUT std_logic;            -- the memory is almost out
    FullMem     :   OUT std_logic;                          -- the memory is full in the FIFO
    dataOut     :   OUT std_logic_vector(7 downto 0);     -- data output
    sel         :   INOUT std_logic_vector(2 downto 0);     -- select output for mux
    FinishedOut :   OUT std_logic;                  -- the FIFO has finished sending out the data
clkOut      :   INOUT std_logic := '0'          -- the clock that the output data is using
);
 end FIFOClockOut;

  architecture architecture_FIFOClockOut of FIFOClockOut is
  -- signal, component etc. declarations
  type ram_t is array (0 to 4095) of std_logic_vector(7 downto 0);                -- The memory for the FIFO
signal ram: ram_t;
signal counterIn    : integer;                -- counter for input
signal counterOut   : integer;                -- counter for output
signal counterClock : std_logic_vector(2 downto 0);                -- counter for clock
signal FullMemBuff  : std_logic;
signal FinishedOutBuff: std_logic;
begin
process(clk)
begin
--there is some more code here which does not use dataOut
if (clk='1') then
    if (FullMemBuff = '0') then 
        if (EnableWr = '1') then
                ram(counterIn)<= dataIn;
                counterIn   <= counterIn + 1;
                end if;
            end if;
if(clkOut ='1') then
    if (FinishedOutBuff = '0') then
            counterClock <= counterClock + "1";
                sel     <= sel+"1";
                end if;
    if (counterClock = "111") then
            if (FinishedOutBuff = '0') then
                    dataOut       <=  ram(counterOut);
                    counterOut    <=  counterOut+1;
            if (counterIn <= (counterOut)) then
                FinishedOutBuff <= '1';
                sel<= "111";
                dataOut <= "00000000";
                end if;     
            else
            dataOut      <=   "00000000";
            sel          <=   "111";
            end if;
                end if;
    end if;
    end if;

   end process;
   end architecture_FIFOClockOut;

Thank you for the help. I am using Libero Polar Fire to code the vhdl and create the rtl. I have simulated the code and it works as expected and provides the correct output. Please ask questions if something is unclear or want more of the code.

Answer 1

So I fixed this by adding a buffer signal in the beginning of the code and setting the DataOut value equal to the DataOut buffer. Not quite sure why this worked, but it fixed it. If any one knows why I would love to know.